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12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)
Napa, California
April 20-April 23
ISBN: 0-7695-2230-0
ASCII Text
x 
 
Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak, "An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 310-311, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004.
 
 
BibTex
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@article{ 10.1109/FCCM.2004.16,
author = {Warren J. Gross and Frank R. Kschischang and P. Glenn Gulak},
title = {An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding},
journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on},
volume = {0},
year = {2004},
isbn = {0-7695-2230-0},
pages = {310-311},
doi = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.16},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
TI - An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
SN - 0-7695-2230-0
SP310
EP311
A1 - Warren J. Gross,
A1 - Frank R. Kschischang,
A1 - P. Glenn Gulak,
PY - 2004
KW - null
VL - 0
JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
ER -
 
Warren J. Gross, McGill University, Montreal, Canada
Frank R. Kschischang, University of Toronto, Canada
P. Glenn Gulak, University of Toronto, Canada
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision Reed-Solomon decoding algorithm. The key feature is the embedding of both a binary tree and a linear array into a two-dimensional array processor, enabling fast polynomial evaluation operations. An FPGA interpolation processor was implemented and demonstrated at a clock frequency of 23 MHz, corresponding to decoding rates of 10-15 Mbps.
Citation:
Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak, "An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding," fccm, pp.310-311, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004
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