A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA

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12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA (PDF)

Napa, California

April 20-April 23

ISBN: 0-7695-2230-0

	ASCII Text	x
	Alireza Hodjat, Ingrid Verbauwhede, "A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 308-309, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004.

	BibTex	x
	@article{ 10.1109/FCCM.2004.1, author = {Alireza Hodjat and Ingrid Verbauwhede}, title = {A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2230-0}, pages = {308-309}, doi = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.1}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA SN - 0-7695-2230-0 SP308 EP309 A1 - Alireza Hodjat, A1 - Ingrid Verbauwhede, PY - 2004 KW - null VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

Alireza Hodjat, University of California, Los Angeles

Ingrid Verbauwhede, University of California, Los Angeles

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2004.1

This paper presents the architecture of a fully pipelined AES encryption processor on a single chip FPGA. By using loop unrolling and inner-round and outer-round pipelining techniques, a maximum throughput of 21.54 Gbits/s is achieved. A fast and area efficient composite field implementation of the byte substitution phase is designed using an optimum number of pipeline stages for FPGA implementation. A 21.54 Gbits/s throughput is achieved using 84 Block RAMs and 5177 Slices of a VirtexII-Pro FPGA with a latency of 31 cycles and throughput per area rate of 4.2 Mbps/Slice.

Citation:

Alireza Hodjat, Ingrid Verbauwhede, "A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA," fccm, pp.308-309, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004

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