Hardware implementation of arithmetic modules is a time-consuming task. Consequently, there is a demand for CAD tools that help the designer in reducing design times. This paper presents a floating-point module generator that allows user specification of the mantissa, exponent bit-width and clock period. This tool generates synthesizable VHDL code in a readable format that can be modified by the designer. It also optimizes circuit performance, providing modules with high-speed execution times, that are comparable to those of existing specific implementations.