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12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04)
FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit
Napa, California
April 20-April 23
ISBN: 0-7695-2230-0
Christopher C. Doss, North Carolina A & T State University, Greensboro, NC
Robert L. Riley, Jr., Air Force Research Laboratory, Eglin AFB, FL
This work explores the feasibility of implementing a floating-point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The project included creating pipelined submodules for implementing basic IEEE-754 single precision operations such as addition, multiplication, and division by 32. These modules were then linked together to form the overall unit. The designs were synthesized, placed and routed. Results indicate that today's FPGAs are well suited for this operation.
Citation:
Christopher C. Doss, Robert L. Riley, Jr., "FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit," fccm, pp.229-238, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'04), 2004
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