We describe a unified approach to scheduling point-to-point uni-directional communications among concurrent FPGA-based hardware processes. In this model, processes have separate address spaces, and share data through communication. Once a channel is written, it may not be re-written until the receiving process reads the data. Thus if the writer process is ready before the reader has read the previous message, the writer must stall. We present an algorithm to automatically generate synchronized hardware schedules for the parallel processes that communicate, so that hardware stall management is not required. The algorithm requires that the parallel processes conform to certain constraints in program control structures and communications forms. If the processes do not conform to these requirements, hardware-supported stall mechanisms are used. We quantify the impact in area and clock speed between compiler-generated synchronization of process schedules and run-time, hardware-mediated synchronization.