In this paper, we explore two important latency issues associated with using an embedded processor as an assistant to programmable logic within a logic-centric system implemented on a platform FPGA. The context is that of the 'software decelerator' - a term introduced by the authors in 2003 to describe a logic-centric counterpart of the familiar hardware accelerator. We first focus on minimizing latency in the logic-processor interface, introducing an efficient interrupt-driven control mechanism. Then, in the context of a case study on packet address lookup, we focus on minimizing latency in memory interfaces, using the processor's hardware cache mechanism for assistance.