This paper gives a design framework for the implementation of the 2-D Orthogonal Discrete Wavelet Transform (DWT) on FPGA. The architecture is based on the Pyramid Algorithm Analysis. It maps spatially the multistage filter banks of the DWT on Xilinx Virtex-e FPGA family using on chip buffering. The architecture takes advantage from the low rate of the high transform stages to reuse the logic. In this paper, we propose a novel FIR structure to handle the computation along the borders using symmetry extension, a new BlockRam configuration for multi ports shift register, and a new mathematical approach to predict and reduce the error dynamic range due to wordlength rounding. For an MxM image size input, our architecture has a period of M² clock cycles, and requires the minimum storage size. The architecture is highly scalable for different filter lengths and number of octaves. The implementation results for a specific 2-D Daubechies-4 Wavelet transform are included.