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11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets
Napa, California
April 09-April 11
ISBN: 0-7695-1979-2
Michael Wirthlin, Brigham Young University, Provo, UT
Eric Johnson, Brigham Young University, Provo, UT
Nathan Rollins, Brigham Young University, Provo, UT
Michael Caffrey, Los Alamos National Laboratory, Los Alamos, NM
Paul Graham, Los Alamos National Laboratory, Los Alamos, NM
FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-earth orbit, FPGAs are susceptible to Single-Event Upsets (SEUs). In an effort to understand the effects of SEUs, an SEU simulator based on the SLAAC-1V computing board has been developed. This simulator artifically upsets the configuration memory of an FPGA and measures its impact on FPGA designs. The accuracy of this simulation environment has been verified using ground-based radiation testing. This simulation tool is being used to characterize the reliability of SEU mitigation techniques for FPGAs.
Citation:
Michael Wirthlin, Eric Johnson, Nathan Rollins, Michael Caffrey, Paul Graham, "The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets," fccm, pp.133, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003
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