Accelerating Bit Error Rate Testing Using a System Level Design Tool

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11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Napa, California

April 09-April 11

ISBN: 0-7695-1979-2

	ASCII Text	x
	V. Singh, A. Root, E. Hemphill, N. Shirazi, J. Hwang, "Accelerating Bit Error Rate Testing Using a System Level Design Tool," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 62, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003.

	BibTex	x
	@article{ 10.1109/FPGA.2003.1227242, author = {V. Singh and A. Root and E. Hemphill and N. Shirazi and J. Hwang}, title = {Accelerating Bit Error Rate Testing Using a System Level Design Tool}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {2003}, issn = {1082-3409}, pages = {62}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.2003.1227242}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Accelerating Bit Error Rate Testing Using a System Level Design Tool SN - 1082-3409 SP EP A1 - V. Singh, A1 - A. Root, A1 - E. Hemphill, A1 - N. Shirazi, A1 - J. Hwang, PY - 2003 KW - null VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

V. Singh, Xilinx Inc.

A. Root, Xilinx Inc.

E. Hemphill, Xilinx Inc.

N. Shirazi, Xilinx Inc.

J. Hwang, Xilinx Inc.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.2003.1227242

System level design tools for creating DSP designs reduce the amount of time needed to create a DSP design, in part by eliminating the need for verification between system model and hardware implementation. The design is developed within a high level modeling environment. This description is compiled into a hardware description language, and synthesized by traditional FPGA tools. The use of system level tools can eliminate the need for an extensive hardware knowledge. This paper demonstrates how such tools can be used to build a Bit Error Rate (BER) tester, and how hardware co-simulation of the entire system provided a 10,000x speed-up over a pure software simulation.

Citation:

V. Singh, A. Root, E. Hemphill, N. Shirazi, J. Hwang, "Accelerating Bit Error Rate Testing Using a System Level Design Tool," fccm, pp.62, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003

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