A crossbar switch with 928 inputs and 928 outputs is presented. Switching elements are constructed using logic in the routing fabric. This approach yields a 16X improvement in logic density compared with using conventional logic. Normally the routing is fixed. However, in FPGAs, the interconnect is defined by the state of SRAM configuration cells, which are dynamically modifiable. Therefore, the switch is implemented on an FPGA using partial configuration to modify routing resources during operation. All paths are synchronously clocked at 155.5 MHz, creating a total throughput of 144.3 GBits/s. To maintain constant clock latency across all paths, partially configurable delay registers are used. Finally, to enable fast switch updates, the partial reconfiguration controller is implemented in hardware.