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10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'02)
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy
Napa, California
September 22-September 24
ISBN: 0-7695-1801-X
Greg Stitt, University of California at Riverside
Brian Grattan, University of California at Riverside
Jason Villarreal, University of California at Riverside
Frank Vahid, University of California at Riverside and University of California at Irvine
We examine the energy savings possible by remapping critical software loops from a microprocessor to configurable logic appearing on the same-chip in commodity chips now commercially available. That logic is typically intended to implement peripherals and coprocessors without increasing chip count — but we show that reduced software energy is an additional benefit, making such chips even more useful. We find critical software loops and re-implement them in the configurable logic such that a repeating software task completes sooner, allowing us to put the system in a low-power state for longer periods, thus reducing energy. We use simulations and estimations for a hypothetical device having a 32-bit MIPS processor plus configurable logic, yielding energy savings of 25%, increasing to 39% assuming voltage scaling. We physically measured several examples running on two commercial single-chip devices having an 8-bit 8051 microprocessor plus configurable logic and a 32-bit ARM microprocessor with configurable logic, with energy savings of 71% and 53% respectively, increasing to an estimated 89% and 75% assuming voltage scaling.
Citation:
Greg Stitt, Brian Grattan, Jason Villarreal, Frank Vahid, "Using On-Chip Configurable Logic to Reduce Embedded System Software Energy," fccm, pp.143, 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'02), 2002
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