This paper presents the architecture of a Reconfigurable Array Media Processor (RAMP). RAMP features a 2-D array of coarse-grained configurable logic blocks (CLBs) connected together by local and global inter-connects. The CLBs on RAMP provide a 4-bit ALU, 2x2 bit parallel multiply function, 4-bit barrel-shifter, two 4-bit registers and a local programmable control unit. RAMP is capable of partial run-time reconfiguration and supports block-mode reconfiguration.The novel features of this device include two programmable high-speed clocks available to each CLB, scalable parallel multiplier, and on-chip memory/registers. RAMP can be used to implement high-performance computational kernels of video, audio and signal processing functions. Matrix multiplication, FIR filters and Inverse DCT functions are used as examples to demonstrate the capabilities of the RAMP architecture.