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Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines Napa California April 21-April 23 ISBN: 0-7695-0375-6 Table of Contents
Joco M.P. Cardoso, INESC/University of Algarve
Horacio C. Neto, INESC/IST pp. 2
A CAD Suite for High-Performance FPGA Design (Abstract)
Brad Hutchings, Brigham Young University
Peter Bellows, Brigham Young University
Joseph Hawkins, Brigham Young University
Scott Hemmert, Brigham Young University
Brent Nelson, Brigham Young University
Mike Rytting, Brigham Young University pp. 12
Formal Verification of Reconfigurable Cores (Abstract)
Satnam Singh, Xilinx Incorporated
Carl Johan Lillieroth, Prover Technology and Chalmers University of Technology pp. 25
Toshiaki Miyazaki, NTT Network Innovation Laboratories
Takahiro Murooka, NTT Network Innovation Laboratories
Masaru Katayama, NTT Network Innovation Laboratories
Atsushi Takahara, NTT Network Innovation Laboratories pp. 34
Jason R. Hess, Virginia Tech
David C. Lee, Virginia Tech
Scott J. Harper, Virginia Tech
Mark T. Jones, Virginia Tech
Peter M. Athanas, Virginia Tech pp. 44
Markus Weinhardt, Imperial College
Wayne Luk, Imperial College pp. 52
Maya B. Gokhale, Sarnoff Corporation
Janice M. Stone, Sarnoff Corporation pp. 63
Parallelizing Applications into Silicon (Abstract)
Jonathan Babb, Massachusetts Institute of Technology
Martin Rinard, Massachusetts Institute of Technology
Csaba Andras Moritz, Massachusetts Institute of Technology
Walter Lee, Massachusetts Institute of Technology
Matthew Frank, Massachusetts Institute of Technology
Rajeev Barua, Massachusetts Institute of Technology
Saman Amarasinghe, Massachusetts Institute of Technology pp. 70
Michael R. Piacentino, Sarnoff Corporation
Gooitzen S. vanderWal, Sarnoff Corporation
Michael W. Hansen, Sarnoff Corporation pp. 82
Bernardo Kastrup, Philips Research Laboratories
Arjan Bink, Philips Research Laboratories
Jan Hoogerbrugge, Philips Research Laboratories pp. 92
CPR: A Configuration Profiling Tool (Abstract)
Srihari Cadambi, Carnegie Mellon University
Seth Copen Goldstein, Carnegie Mellon University pp. 104
Nicholas McKay, University of Glasgow
Satnam Singh, Xilinx Incorporated pp. 114
Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems (Abstract)
Milan Vasilko, Bournemouth University
David Cabanis, Bournemouth University pp. 123
W. Luk, Imperial College
T.K. Lee, Imperial College
J.R. Rice, Imperial College
N. Shirazi, Imperial College
P.Y.K. Cheung, Imperial College pp. 136
Laurent Moll, Compaq Computer Corporation
Mark Shand, Compaq Computer Corporation
Alan Heirich, Compaq Computer Corporation pp. 146
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking (Abstract)
pp. 158
J. Carlos Alves, FEUP/INESC
J. Canas Ferreira, FEUP/INESC
C. Albuquerque, FEUP/INESC
Jose F. Oliveira, FEUP/INESC
J. Soeiro Ferreira, FEUP/INESC
J. Silva Matos, FEUP/INESC pp. 168
Tyler J. Moeller, Massachusetts Institute of Technology
David R. Martinez, Massachusetts Institute of Technology pp. 178
Optimizing FPGA-Based Vector Product Designs (Abstract)
Dan Benyamin, University of California at Los Angeles
John Villasenor, University of California at Los Angeles
Wayne Luk, Imperial College pp. 188
Ronald Laufer, Carnegie Mellon University
R. Reed Taylor, Carnegie Mellon University
Herman Schmit, Carnegie Mellon University pp. 200
Andrew A. Chien, University of California at San Diego
Jay H. Byun, University of Illinois at Urbana-Champaign pp. 209
Mark Jones, Virginia Institute of Technology
Luke Scharf, Virginia Institute of Technology
Jonathan Scott, Virginia Institute of Technology
Chris Twaddle, Virginia Institute of Technology
Matthew Yaconis, Virginia Institute of Technology
Kuan Yao, Virginia Institute of Technology
Peter Athanas, Virginia Institute of Technology
Brian Schott, USC/ISI-East pp. 222
A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms (Abstract)
Gerardo Orlando, GTE Government Systems
Christof Paar, Worcester Polytechnic Institute pp. 232
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping (Abstract)
M.P. Leong, Chinese University of Hong Kong
M.Y. Yeung, Chinese University of Hong Kong
C.K. Yeung, Chinese University of Hong Kong
C.W. Fu, Chinese University of Hong Kong
P.A. Heng, Chinese University of Hong Kong
P.H.W. Leong, Chinese University of Hong Kong pp. 240
Kiran Bondalapati, University of Southern California
Viktor K. Prasanna, University of Southern California pp. 249
J-P Heron, Queen's University of Belfast
R.F. Woods, Queen's University of Belfast pp. 260
A Virtual Hardware Handler for RTR Systems (Abstract)
R. Turner, Queen's University of Belfast
R. Woods, Queen's University of Belfast
S. Sezer, Queen's University of Belfast
J. Heron, Queen's University of Belfast pp. 262
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results (Abstract)
Eric K. Pauer, Sanders, a Lockheed Martin Company
Paul D. Fiore, Sanders, a Lockheed Martin Company
John M. Smith, Sanders, a Lockheed Martin Company pp. 264
V. Sklyarov, Aveiro University
J. Fonseca, Aveiro University
R. Monteiro, Aveiro University
A. Oliveira, Aveiro University
A. Melo, Aveiro University
N. Lau, Aveiro University
I. Skliarova, Aveiro University
P. Neves, Aveiro University
A. Ferrari, Aveiro University pp. 266
Cynthia Cousineau, ?cole Polytechnique de Montr?al
François Laperle, MiroTech MicroSystems Incorporated
Yvon Savaria, ?cole Polytechnique de Montr?al and MiroTech MicroSystems Incorporated pp. 268
Brian Schott, University of Southern California
Chen Chen, University of Southern California
Steve Crago, University of Southern California
Joe Czarnaski, University of Southern California
Matt French, University of Southern California
Ivan Hom, University of Southern California
Tam Tho, University of Southern California
Terri Valenti, University of Southern California pp. 270
Vinoo Srinivasan, University of Cincinnati
Ranga Vemuri, University of Cincinnati pp. 272
Andreas Koch, Technical University of Braunschweig pp. 274
Michael Baxter, Ricoh Silicon Valley pp. 278
Simon D. Haynes, Imperial College of Science, Technology and Medicine
Peter Y. K. Cheung, Imperial College of Science, Technology and Medicine
Wayne Luk, Imperial College of Science, Technology and Medicine
John Stone, Sony Broadcast and Professional Europe pp. 280
Christof Teuscher, Swiss Federal Institute of Technology
Jacques-Olivier Haenni, Swiss Federal Institute of Technology
Hector Fabio Restrepo, Swiss Federal Institute of Technology
Eduardo Sanchez, Swiss Federal Institute of Technology
Francisco J. Gomez, Universidad Autonoma de Madrid pp. 282 pp. 284
Scott Hauck, Northwestern University
William D. Wilson, Northwestern University pp. 286
Jack Jean, Wright State University
Xuejun Liang, Wright State University
Brian Drozd, Wright State University
Karen Tomko, Wright State University pp. 290
Benjamin Levine, University of Tennessee
Senthil Natarajan, University of Tennessee
Chandra Tan, University of Tennessee
Danny Newport, University of Tennessee
Don Bouldin, University of Tennessee pp. 292
Deepali Deshpande, Iowa State University
Arun K. Somani, Iowa State University
Akhilesh Tyagi, Iowa State University pp. 294
On Reconfiguring Cache for Computing (Abstract)
Hue-Sung Kim, Iowa State University
Arun K. Somani, Iowa State University
Akhilesh Tyagi, Iowa State University pp. 296
Ronald D. Williams, University of Virginia
Brian D. Kuebert, University of Virginia pp. 298
Kiarash Barzagan, Northwestern University
Majid Sarrafzadeh, Northwestern University pp. 300
Lijun Gao, University of Minnesota
Sarvesh Shrivastava, University of Minnesota
Hanho Lee, University of Minnesota
Gerald E. Sobelman, University of Minnesota pp. 304
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware (Abstract)
Miron Abramovici, Bell Labs - Lucent Technologies
Jose T. de Sousa, Bell Labs - Lucent Technologies pp. 306
Pak K. Chan, University of California at Santa Cruz
M.J. Boyd, University of California at Santa Cruz
S. Goren, University of California at Santa Cruz
K. Klenk, University of California at Santa Cruz
V. Kodavati, University of California at Santa Cruz
R. Kundu, University of California at Santa Cruz
M. Margolese, University of California at Santa Cruz
J. Sun, University of California at Santa Cruz
K. Suzuki, University of California at Santa Cruz
E. Thorne, University of California at Santa Cruz
X. Wang, University of California at Santa Cruz
J. Xu, University of California at Santa Cruz
M. Zhu, University of California at Santa Cruz pp. 308
Dannie Lau, University of California at Los Angeles
Aaron Schneider, University of California at Los Angeles
Milos D. Ercegovac, University of California at Los Angeles
John Villasenor, University of California at Los Angeles pp. 310
Luiz Maltar, COPPE-Universidade Federal do Rio de Janeiro
Felipe M.G. França, COPPE-Universidade Federal do Rio de Janeiro
Vladimir C. Alves, COPPE-Universidade Federal do Rio de Janeiro
Cláudio L. Amorim, COPPE-Universidade Federal do Rio de Janeiro pp. 312
B?zier Curve Rendering on Virtex(tm) (Abstract)
Donald MacVicar, University of Glasgow
Satnam Singh, Xilinx Incorporated
Robert Slous, Xilinx Incorporated pp. 314 Usage of this product signifies your acceptance of the Terms of Use.
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