A compact fast elliptic curve cryptosystem coprocessor with variable key size is implemented with a Xilinx FPGA. This implementation utilizes the internal SRAM/registers of the FPGA and has the whole system implemented within a single FPGA chip. The compact design helps reduce the overhead and limitations associated with data transfer between FPGA and host, and thus leads to high performance. The experimental data shows that the carefully constructed hardware architecture is regular and has high CLB utilization.