Compilers for VLIW machines may be unable to find instructions to fill every field in every word, and the empty fields waste memory bandwidth and reduce the average number of instructions completed per cycle. Reconfigurable logic can perform a much wider range of tasks than optimized static functional units, but performance speed for any particular task rarely approaches that of custom logic. The basic question addressed by this work was whether the greater hardware utilization offered by reconfigurable functional units could compensate for a reduction in clock rate. This effort found very limited conditions that can yield performance improvement using reconfigurable pipelines when compared with static pipelines. Greater promise was found with instruction set enhancements made possible by the reconfigurable pipelines.