Today's FPGAs are no longer used simply for glue logic. They possess sufficient gate capacity and performance to implement intellectual property (IP) blocks and other complex systems consisting of data paths, control logic, I/O, and memories. System-on-chip designers who target FPGAs are increasingly turning towards reusable IP libraries as a means of coping with increased design complexity[1, 3, 2]. Unfortunately, creating libraries of parametric IP for FPGAs is an arduous task. Despite improvements in algorithmic mapping, placement, and routing, high-performance FPGA circuits often require hand-crafted layout. The design problem is further complicated by the requirement that hand-crafted IP target multiple FPGA families.