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Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
ICARUS: A Dynamically Reconfigurable Computer Architecture
Napa California
April 21-April 23
ISBN: 0-7695-0375-6
ASCII Text
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Michael Baxter, "ICARUS: A Dynamically Reconfigurable Computer Architecture," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 278, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.
 
 
BibTex
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@article{ 10.1109/FPGA.1999.803696,
author = {Michael Baxter},
title = {ICARUS: A Dynamically Reconfigurable Computer Architecture},
journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on},
volume = {0},
year = {1999},
issn = {1082-3409},
pages = {278},
doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803696},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
TI - ICARUS: A Dynamically Reconfigurable Computer Architecture
SN - 1082-3409
SP
EP
A1 - Michael Baxter,
PY - 1999
VL - 0
JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
ER -
 
Michael Baxter, Ricoh Silicon Valley
ICARUS (Image Computing, Automatically Reconfigurable, Unlimited Scale), is an architecture for general purpose parallel computing. The current implementation uses standard FPGAs in novel ways, has no host CPU and differs in many ways from the fixed CPU plus variable FPGA" approach to computing. Different instruction set architectures (ISAs) are loaded automatically during runtime. Two key architectural elements are S-Machines (Symbolic Machines), and T-Machines (Transaction Machines).
Citation:
Michael Baxter, "ICARUS: A Dynamically Reconfigurable Computer Architecture," fccm, pp.278, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999
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