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Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures
Napa California
April 21-April 23
ISBN: 0-7695-0375-6
ASCII Text
x 
 
Vinoo Srinivasan, Ranga Vemuri, "Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 272, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.
 
 
BibTex
x
 
@article{ 10.1109/FPGA.1999.803694,
author = {Vinoo Srinivasan and Ranga Vemuri},
title = {Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures},
journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on},
volume = {0},
year = {1999},
issn = {1082-3409},
pages = {272},
doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803694},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
TI - Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures
SN - 1082-3409
SP
EP
A1 - Vinoo Srinivasan,
A1 - Ranga Vemuri,
PY - 1999
VL - 0
JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
ER -
 
Vinoo Srinivasan, University of Cincinnati
Ranga Vemuri, University of Cincinnati
This paper presents spade , a system for partitioning designs onto multi- fpga architectures. The input to spade is a task graph, that is composed of computational tasks, memory tasks and the communication and synchronization between tasks. spade consists of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization and rtl design space exploration heuristic. We show how various architectural constraints can be effectively handled using an iterative partitioning engine.
Citation:
Vinoo Srinivasan, Ranga Vemuri, "Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures," fccm, pp.272, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999
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