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Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Accelerating Run-Time Reconfiguration on FCCMs
Napa California
April 21-April 23
ISBN: 0-7695-0375-6
ASCII Text
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J-P Heron, R.F. Woods, "Accelerating Run-Time Reconfiguration on FCCMs," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 260, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.
 
 
BibTex
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@article{ 10.1109/FPGA.1999.803688,
author = {J-P Heron and R.F. Woods},
title = {Accelerating Run-Time Reconfiguration on FCCMs},
journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on},
volume = {0},
year = {1999},
issn = {1082-3409},
pages = {260},
doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803688},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
TI - Accelerating Run-Time Reconfiguration on FCCMs
SN - 1082-3409
SP
EP
A1 - J-P Heron,
A1 - R.F. Woods,
PY - 1999
VL - 0
JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
ER -
 
J-P Heron, Queen's University of Belfast
R.F. Woods, Queen's University of Belfast
The paper describes the implementation of the arithmetic operations of multiplication, division and square root on a Xilinx XC6200 FPGA. By using a design approach to enhance similarities across circuits, partial reconfiguration has been used to allow reductions in reconfiguration times of up to 75% on trials using the VCC HOTWorks board.
Citation:
J-P Heron, R.F. Woods, "Accelerating Run-Time Reconfiguration on FCCMs," fccm, pp.260, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999
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