This paper describes the current status of a suite of CAD tools designed specifically for use by designers who are developing high-performance configurable-computing applications. Implemented in Java, these tools are based on an embedded design language referred to as JHDL that allows designers to write Java programs that generate digital circuits. The JHDL suite includes: (1) a graphical debugging tool that allows designers to simulate, debug and hierarchically navigate their designs, (2) a schematic generator that can automatically create a high-quality schematic view of a JHDL description, (3) an EDIF 2.0 netlist class that generates output compatible with current Xilinx M1 place and route software, (4) simulation models and transparent run-time support for the Annapolis Microsystems WildForce platform, and (5) a graphical floorplanner (under development) that will be used cooperatively with the schematic view to manually floor-plan designs. JHDL provides a unified design environment where a single, user interface can be used for both simulation and execution.This allows the designer to request either simulation or execution (or a mixture of the two) using the exact same commands for both. This is a big advantage for designers because they can learn a single debugging environment that works for both simulation and execution --in contrast with current systems where execution and simulation environments are distinct and very different. JHDL is currently being used to design several complex applications in image processing and signal processing.