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IEEE Symposium on FPGAs for Custom Computing Machines
A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures
Napa Valley, California
April 15-April 17
ISBN: 0-8186-8900-5
ASCII Text
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Alexandre F. Tenca, Milos D. Ercegovac, "A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 216, IEEE Symposium on FPGAs for Custom Computing Machines, 1998.
 
 
BibTex
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@article{ 10.1109/FPGA.1998.707899,
author = {Alexandre F. Tenca and Milos D. Ercegovac},
title = {A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures},
journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on},
volume = {0},
year = {1998},
issn = {1082-3409},
pages = {216},
doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1998.707899},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
TI - A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures
SN - 1082-3409
SP
EP
A1 - Alexandre F. Tenca,
A1 - Milos D. Ercegovac,
PY - 1998
VL - 0
JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
ER -
 
Alexandre F. Tenca, Oregon State University
Milos D. Ercegovac, University of California at Los Angeles
This paper presents the organization of an arithmetic unit for variable long-precision (VLP) operands suitable for reconfigurable computing. The reconfigurable arithmetic coprocessor (RAC) cooperates with the host computer in the VLP tasks. The main design issues addressed in the paper are: (a) mapping of the most frequent and time consuming operations of the VLP arithmetic algorithms to RAC, and (b) design of VLP algorithms that allow reduced reconfiguration time between arithmetic operations. The VLP arithmetic algorithms proposed cover multiplication, division and square root. In this paper we present the main building blocks used in the VLP arithmetic circuits, show the similarities of each arithmetic operator and present area/time estimates of these circuits in Xilinx FPGAs.KEYWORD_LIST: long-precision, computer arithmetic, reconfigurable architecture
Citation:
Alexandre F. Tenca, Milos D. Ercegovac, "A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures," fccm, pp.216, IEEE Symposium on FPGAs for Custom Computing Machines, 1998
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