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IEEE Symposium on FPGAs for Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
Napa Valley, California
April 15-April 17
ISBN: 0-8186-8900-5
Maya B. Gokhale, Sarnoff Corp.
Janice M. Stone, Sarnoff Corp.
Hybrid architectures combining conventional processors with configurable logic resources enable efficient coordination of control with datapath computation. With integration of the two components on a single device, loop control and data-dependent branching can be handled by the conventional processor, while regular datapath computation occurs on the configurable hardware. This paper describes a novel pragma-based approach to programming such hybrid devices. The NAPA C language provides pragma directives so that the programmer (or an automatic partitioner) can specify where data is to reside and where computation is to occur with statement-level granularity. The NAPA C compiler, targeting National Semiconductor's NAPA1000 chip, performs semantic analysis of the pragma-annotated program and co-synthesizes a conventional program executable combined with a configuration bit stream for the adaptive logic. Compiler optimizations include synthesis of hardware pipelines from pipelineable loops.
Citation:
Maya B. Gokhale, Janice M. Stone, "NAPA C: Compiling for a Hybrid RISC/FPGA Architecture," fccm, pp.126, IEEE Symposium on FPGAs for Custom Computing Machines, 1998
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