Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme

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Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00)-Volume 2

Maastricht, The Netherlands

September 05-September 07

ISBN: 0-7695-0780-8

	ASCII Text	x
	Rong Lin, "Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme," EUROMICRO Conference, vol. 2, pp. 2456, Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00)-Volume 2, 2000.

	BibTex	x
	@article{ 10.1109/EURMIC.2000.874531, author = {Rong Lin}, title = {Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme}, journal ={EUROMICRO Conference}, volume = {2}, year = {2000}, isbn = {0-7695-0780-8}, pages = {2456}, doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.2000.874531}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - EUROMICRO Conference TI - Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme SN - 0-7695-0780-8 SP EP A1 - Rong Lin, PY - 2000 KW - Arithmetic circuit KW - parallel counter and compressor KW - partial product reduction KW - low power high performance CMOS circuit design KW - VLSI design VL - 2 JA - EUROMICRO Conference ER -

Rong Lin, State University of New York at Geneseo

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EURMIC.2000.874531

This paper presents a novel approach for CMOS low-power, high performance parallel multiplier design, utilizing a recently proposed binary shift switch logic scheme. Compared with the existing well-known parallel multiplier designs, the new approach requires fewer partial product bit reduction stages, and improves performance in speed, VLSI area as well as power dissipation. SPICE simulations with a 0.25-micron, 2.5-volt supply process on critical paths have demonstrated the superiority of the approach.

Index Terms:

Arithmetic circuit, parallel counter and compressor, partial product reduction, low power high performance CMOS circuit design, VLSI design

Citation:

Rong Lin, "Parallel Multiplier Designs Utilizing A Non-Binary Logic Scheme," euromicro, vol. 2, pp.2456, Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00)-Volume 2, 2000

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