The Filter Data Cache scheme introduces two independent L1 data caches with different organizations placed in parallel. In this scheme, each cache block has a small counter attached for storing information needed for management - called reuse information. The Filter Data Cache micro-architecture offers lower miss rates and better speedups than conventional organizations; as well as saving die area. The reuse information included is directly responsible for improving the overall cache hit-ratio and reducing bus utilization, and this makes it relevant for multiprocessor systems. In this paper, we show how the reuse information of the Filter Data Cache scheme can also be used to design competitive coherence protocols tailored to that scheme. These offer better performance results than traditional write-invalidate and write-update policies.