Field Programmable Gate Arrays (FPGAs) are the most flexible solutions for reconfigurable platforms. However, they do not always deliver the required performance, e.g. in base-band processing, where the trend is to use DSP processors for flexibility and very specialized ASICs for performance. We propose a reconfigurable architecture based on parameterized functional blocks that correspond to core functionality of the base-band systems. This architecture competes with DSPs and ASICs in both flexibility and performance. Our methodology starts with a systematic analysis of various base-band standards. We derived functional specification of the required blocks and identified the data flows to be reflected in the interconnect fabric. The parameterized blocks are of higher complexity and performance than the cells in FPGAs. Based on our analysis, we can take advantage of the sequential data flow in the base-band applications and provide dedicated circuitry to support signal multiplexing between blocks to fully utilise the bandwidth on the data path, conserve chip area and simplify inter-chip connections with route-through resources.