Wire capacitance models used in synthesis tools are typically based on number of fanouts. These wire capacitance models can be misleading when compared to real wiring. This discrepancy can cause synthesis tools to optimize incorrectly causing severe problems with chip level timing convergence. Designs may take longer than expected and designers may work on timing paths that are not critical thus increasing the design cycle. In submicron designs, it is crucial to improve the timing convergence between synthesis and physical design. This paper describes several practical approaches used in timing convergence of an advanced PowerPC 1 microprocessor. The impact of each approach is evaluated on the timing and size of the microprocessor.