This paper investigates different architectures implementing bit-parallel constant coefficient multiplication in FPGA structures. At first, the multiplier-less multiplication (MM) architectures employing Canonic Sign Digit (CSD) and substructure sharing methods are addressed, and a novel algorithm for the conversion from two's complement to CSD representation is presented. In the second part of this paper the Look up table, based Multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture considers also reduction of the address width for each memory cell and the possibility of memory substructure sharing. Finally, the implementation results for Xilinx XC4000 and Virtex families are presented. As a result, the MM generally surpasses the LM architecture, however the actual choice between these two architectures is coefficient and input parameters dependent.