loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00) Volume I-Volume 1
Testability of Circuits Derived from Lattice Diagrams
Maastricht, The Netherlands
September 05-September 07
ISBN: 0-7695-0780-8
Rolf Drechsler, Albert-Ludwigs-University
Wolfgang Günther, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
In this paper the testability of circuits derived from BDDs representing totally symmetric functions is analyzed. A test pattern generation technique is presented that has runtime linear in the size of the BDD. The result is directly applicable to circuits derived from lattice diagrams, a new design style that combines the synthesis and the layout step. Experimental results show that complete test generation for functions with more than 500 variables can be done in less than one CPU second.
Citation:
Rolf Drechsler, Wolfgang Günther, Bernd Becker, "Testability of Circuits Derived from Lattice Diagrams," euromicro, vol. 1, pp.1188, Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00) Volume I-Volume 1, 2000
Usage of this product signifies your acceptance of the Terms of Use.