The objective of the technology mapping method presented in this paper is to cover a multiple-output function by a minimal number of PAL-based logic blocks included in CPLDs. According to this method product terms included in a logic block can be shared by several functions. Developed algorithms, implemented within the PALDec system, have been used for partitioning the benchmark circuits due to implementation by means of the PAL-based logic blocks with the restricted number of terms. The results are compared to the classical technology mapping method and synthesis of benchmarks executed by means of MACHXL and MAX+PLUS II software.