Most CPLD architectures include PAL-based logic blocks containing a limited number of terms connected to the individual output macro-cell. These blocks often contain three-state output buffers. Appropriate partition of whole devices into suitable logic blocks is one of the basic problems of the synthesis process. A method for logic synthesis based on decomposition for a PAL-based logic block with three-state output buffers is presented in this paper. Decomposition is the main element and first step of the synthesis process. Fundamental to PAL-oriented decomposition is the Curtis theory. The constrained decomposition algorithm is based on a proposed PAL-oriented graph colouring. Additionally, the method of two-level logic synthesis, which makes use of three-state output buffers, is used for implemented free and bound logic blocks. Experimental results are compared to previously published methods and firmware tools are given to show the efficiency of this approach.