Boolean equivalence checking has turned out to be a powerful method for verifying combinational circuits and is already an integrated part of the design cycle. If equivalence checking fails, Design Error Diagnosis and Correction (DEDC) are performed which can locate and correct design errors fully automatically in many cases. However, DEDC algorithms always have to consider the circuit as a whole and cannot be applied locally to a small sub portion of the design. Thus, the size of rectifiable circuits is often limited which is a hard restriction for applying DEDC in industrial environments. In this paper, we address the problem of how to make DEDC applicable to larger circuits. We show how a small sub circuit can be safely extracted from a bigger circuit under consideration of its environment. Our extraction method surrounds the extracted component with automatically derived logic such that the rectification of the newly constructed, much smaller circuit yields the same results as rectifying the original, much bigger circuit. In addition, we compare the extraction method with the circuit abstraction method presented in [11].