Time multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of time multiplexing makes it possible to reduce the size of FPGA's but requires a new step in the design flow. The circuit has to be divided into sequential steps, partitions. In this paper, we present an algorithm, which partitions sequential circuits for time multiplexing. The algorithm is based on list scheduling. Our experiments show that the algorithm is fast. It is able to partition a design with 4000 nodes in less than 4 seconds. The generated partitions have small size overhead, up to 3.2%, while no time overhead is allowed, besides the necessary reconfiguration time.