This paper reports on design decisions taken in the modeling, design and implementation of a full set of versions of SPARC v8 Integer Unit and gives data about the experimental results obtained. VHDL has been the description language, Synopsys tools those for the logical synthesis, and Duet Technologies' Epoch has been used for the physical layout of the final circuits. These have been carried out in a 0.35 um, three metal layers CMOS process. The description strategy and the design flow methodology allow to obtain quantitative results that characterize suitable points in the design space. They show how much microarchitecture, design, data path granularity and module decisions affect performance and cost functions. This design space exploration down to physical layouts is made possible by modeling techniques based on configurable VHDL descriptions.