Through this paper a multiplier unit has been presented focussing on its reusability aspects. The device accepts any external size for the operand multiplier (X), although internally only sizes being two's powers are considered. To render the partial-product addition time independent on the number of bits of the adders redundant binary adders have been selected, as they are carry-free. This ensures that the addition time in each of the layers of the adder tree will remain independent of the adder size. The results from synthesis are being improved using more up-to-date design libraries. The DfR phase consisted in the algorithmic specification in VHDL, code debugging and simulation. These tasks and the production of the results presented for the eight cases studied took four weeks of a junior engineer's workforce.