A digital VLSI implementation of an algorithm modeling the "effective" signal processing of the human auditory system is presented. The model consists of several stages psychoacoustically and physiologically motivated by the signal processing in the human ear and was successfully applied to various speech processing applications. The processing scheme was partitioned for implementation in a set of three chips. Due to local properties of the signal dynamic and the necessary arithmetical precision different approaches for number representation and appropriate arithmetic operators were investigated and implemented. It is demonstrated how an application of the model has been used to determine the necessary word lengths for a transfer of the algorithm into a version suitable for hardware implementation. Fix point arithmetic is used in the linear parts of the origin algorithm and a special small floating point operator set was developed for the nonlinear part. This part was coded in behavioral VHDL and synthesized with Synopsys Behavioral Compiler. The hardware algorithm is being evaluated on different implementation levels for a FPGA and will be manufactured as ASICs in a later version. The presented FPGA chip set will be combined with a commercial DSP system (TMS320C6201) for real time and reconfigurable signal processing.