Memory hierarchy has been accepted as the most limiting factor in current MII processors [1]. For architectures that employ static instruction scheduling, memory performance is of increasing importance, since the instruction scheduling process tends to increase code size. This paper looks at the impact of a realistic memory hierarchy on a minimal superscalar processor model which uses aggressive static instruction scheduling techniques. The divergent performance impact of a cache on scheduled and unscheduled code is quantified, as well as the resultant effect on overall scheduling speed-up.