This paper presents an approach to power analysis in gate-level controllers. It is assumed that the power consumption depends on the number of signal value changes during a pattern switch.

A probabilistic model for analyzing the power consumption for a given circuit is shown together with a power simulation approach. Weak parts of the probabilistic model are pointed out. Furthermore the impact of applying optimization technology based on redundancy addition and removal technique to power consumption is analyzed.

Experimental results show results of benchmark circuits with respect to the probabilistic model and give a save potential for the circuits.