This work combines FPGA placement and global routing phases in a single one, taking advantage of the interrelations between both. We have developed Rectilinear Steiner Regions (RSR), a new fast algorithm to approximate the Rectilinear Steiner Minimum Tree (RSMT) of each multiterminal net. The search of placement solutions is performed in three Simulated Annealing optimization phases, guided by different objective functions. The first one uses semiperimeter classic metric to reduce the length of the nets. The second one estimates more precisely the length of the nets with RSR algorithm. The third stage measures the congestion making a fast routing of RSR regions in each placement iteration. We have also developed an RSR-based global router. This optimization method has been applied for the placement and global routing of a set of benchmark circuits. The layouts obtained, require equal or fewer routing tracks per channel segment than those produced by other tools appeared in the literature, that only optimize the semiperimeter classic placement cost function.