For the design of a digital system for real-time applications it is necessary to get early and proper estimates of the timing constraints. These are normally obtained by the designer by synthesis on system level. On this level it is decided which part of an algorithm is implemented by application specific hardware and which by software performed by standard processors. Hardware resources are modeled without detailed functionality and software utilizes the resources. Partitioning at the system-level means to determine a heterogeneous multiprocessor system and a mapping of tasks on the system components. In this paper we describe our system-level synthesis tool which supports the development of devices which need a digital system to perform tasks in real-time (based on a formal model). The efficiency of the tool, which has been fully implemented and tested, is demonstrated using large practical examples.