Tolerance to faults in processing arrays can be achieved-even for run time faults-by means of reconfiguration techniques that exploit architectural regularity to achieve high probability of survival with reduced redundancy and satisfying constraints on path length and interconnection channel width. These two last factors in fact limit reconfiguration efficiency, by imposing constraints on number and organization of spare elements. A partitioning approach is presented that allows us to overcome such limitations leading to high probability of survival even in the presence of "critical" fault patterns.