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23rd EUROMICRO Conference '97 New Frontiers of Information Technology
High performance in tree-based parallel architectures
Budapest, HUNGARY
September 01-September 04
ISBN: 0-8186-8129-2
ASCII Text
x 
 
F. Ancona, S. Rovetta, R. Zumino, "High performance in tree-based parallel architectures," EUROMICRO Conference, pp. 474, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997.
 
 
BibTex
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@article{ 10.1109/EURMIC.1997.617358,
author = {F. Ancona and S. Rovetta and R. Zumino},
title = {High performance in tree-based parallel architectures},
journal ={EUROMICRO Conference},
volume = {0},
year = {1997},
issn = {1089-6503},
pages = {474},
doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617358},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - EUROMICRO Conference
TI - High performance in tree-based parallel architectures
SN - 1089-6503
SP
EP
A1 - F. Ancona,
A1 - S. Rovetta,
A1 - R. Zumino,
PY - 1997
KW - performance evaluation; high performance; tree-based parallel architectures; integrated schema; complex node; dual-port memory; bidirectional high-speed communication link; tree-structured processor hierarchies; optimality; connectivity; memory speed; transputers; experimental development; associative models
VL - 0
JA - EUROMICRO Conference
ER -
 
F. Ancona, Genoa Univ., Italy
S. Rovetta, Genoa Univ., Italy
R. Zumino, Genoa Univ., Italy
The integrated schema called "complex node" couples twin processors, which share a dual-port memory supporting a bidirectional, high-speed communication link. The paper considers the contribution of this device to tree-structured processor hierarchies. As shown by theoretical analysis, increased complex node performance may ensure optimality under reasonable conditions in terms of connectivity and memory speed, which can be easily attained by commercial equipment. This endows the overall research with additional value from a technical point of view. The integrated approach has been implemented by using transputers for experimental development; related advantages in a specific application (implementation of associative models) are also highlighted.
Index Terms:
performance evaluation; high performance; tree-based parallel architectures; integrated schema; complex node; dual-port memory; bidirectional high-speed communication link; tree-structured processor hierarchies; optimality; connectivity; memory speed; transputers; experimental development; associative models
Citation:
F. Ancona, S. Rovetta, R. Zumino, "High performance in tree-based parallel architectures," euromicro, pp.474, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997
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