Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces

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	Similar Articles Articles by A. Pavlov Articles by J.L. Bechennec Articles by D. Etiemble

23rd EUROMICRO Conference '97 New Frontiers of Information Technology

Budapest, HUNGARY

September 01-September 04

ISBN: 0-8186-8129-2

	ASCII Text	x
	A. Pavlov, J.L. Bechennec, D. Etiemble, "Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces," EUROMICRO Conference, pp. 409, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997.

	BibTex	x
	@article{ 10.1109/EURMIC.1997.617340, author = {A. Pavlov and J.L. Bechennec and D. Etiemble}, title = {Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces}, journal ={EUROMICRO Conference}, volume = {0}, year = {1997}, issn = {1089-6503}, pages = {409}, doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617340}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - EUROMICRO Conference TI - Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces SN - 1089-6503 SP EP A1 - A. Pavlov, A1 - J.L. Bechennec, A1 - D. Etiemble, PY - 1997 KW - memory architecture; performance evaluation; memory hierarchy simulation; desktop PC; commodity chips; PC microcomputers; synthetic bus traces; dynamically scheduled superscalar microprocessor VL - 0 JA - EUROMICRO Conference ER -

A. Pavlov, Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France

J.L. Bechennec, Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France

D. Etiemble, Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617340

We present a methodology to evaluate performance of the memory hierarchy of PC microcomputers. This methodology is based on synthetic bus traces which allow simulation of the memory hierarchy without having to build a model of the microprocessor. As a result, the simulation is orders of magnitude faster than an instruction level one but the methodology is not valid with a dynamically scheduled superscalar microprocessor.

Index Terms:

memory architecture; performance evaluation; memory hierarchy simulation; desktop PC; commodity chips; PC microcomputers; synthetic bus traces; dynamically scheduled superscalar microprocessor

Citation:

A. Pavlov, J.L. Bechennec, D. Etiemble, "Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces," euromicro, pp.409, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997

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