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23rd EUROMICRO Conference '97 New Frontiers of Information Technology
Complete x86 instruction trace generation from hardware bus collect
Budapest, HUNGARY
September 01-September 04
ISBN: 0-8186-8129-2
ASCII Text
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P. Bosch, A. Carloganu, D. Etiemble, "Complete x86 instruction trace generation from hardware bus collect," EUROMICRO Conference, pp. 402, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997.
 
 
BibTex
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@article{ 10.1109/EURMIC.1997.617339,
author = {P. Bosch and A. Carloganu and D. Etiemble},
title = {Complete x86 instruction trace generation from hardware bus collect},
journal ={EUROMICRO Conference},
volume = {0},
year = {1997},
issn = {1089-6503},
pages = {402},
doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617339},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - EUROMICRO Conference
TI - Complete x86 instruction trace generation from hardware bus collect
SN - 1089-6503
SP
EP
A1 - P. Bosch,
A1 - A. Carloganu,
A1 - D. Etiemble,
PY - 1997
KW - computer architecture; complete x86 instruction trace generation; hardware bus collect; architectural improvements; microprocessors; memory hierarchies; trace driven simulation; benchmark traces; performance data; hardware/software approach; x86 execution traces; commercial analyzer
VL - 0
JA - EUROMICRO Conference
ER -
 
P. Bosch, Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France
A. Carloganu, Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France
D. Etiemble, Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France
Studying architectural improvements for microprocessors and their memory hierarchies and evaluating the corresponding performance generally need trace driven simulation. Hardware is modeled, benchmark traces are generated and applied to the model and performance data is measured and analyzed. We present a hardware/software approach to collect perfect x86 execution traces using a commercial analyzer.
Index Terms:
computer architecture; complete x86 instruction trace generation; hardware bus collect; architectural improvements; microprocessors; memory hierarchies; trace driven simulation; benchmark traces; performance data; hardware/software approach; x86 execution traces; commercial analyzer
Citation:
P. Bosch, A. Carloganu, D. Etiemble, "Complete x86 instruction trace generation from hardware bus collect," euromicro, pp.402, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997
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