We present a new ASIC design process including software/hardware Co-simulation. The increasing complexity of software/hardware systems means that the design process takes more time and today the verification is often the bottle neck in the design process. For example, synthesis tools have drastically reduced the design time for ASIC's and therefore the verification now occupies a larger proportion of the entire design process time. In many software/hardware applications, Co-simulation can considerably reduce the verification time for the ASIC. This article will describe and discuss today's verification methods and describe the new Co-simulation design process for ASICs.