Proceedings of the 22nd EUROMICRO Conference Load Balancing in Superscalar Architectures Prague, Czech Republic September 02-September 05 ISBN: 0-8186-7487-3
Abstract: New techniques are increasing the degree of instruction-level parallelism exploited by processors. Recent superscalar implementations include multiple functional units, allowing the parallel execution of several instructions from the same application program. The trend towards an expansion of the number of hardware resources is likely to continue in future superscalar designs, and in order to maximize the processor throughput, the computational load must be balanced among these resources by the dynamic instruction-issuing algorithm. We investigate the effect on performance caused by the way instructions are distributed among the functional units of superscalar processors. Our results show that a performance gain of up to 38% can be obtained when the instructions are evenly distributed among the functional units.
Index Terms:
parallel architectures; superscalar architectures; load balancing; instruction-level parallelism; multiple functional units; parallel instruction execution; application program; hardware resources; processor throughput; computational load; dynamic instruction-issuing algorithm; performance; superscalar processors
Citation:
E.M.C. Filho, E.S.T. Fernandes, A. Wolfe, "Load Balancing in Superscalar Architectures," euromicro, pp.0651, Proceedings of the 22nd EUROMICRO Conference, 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb