Load Balancing in Superscalar Architectures

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by E.M.C. Filho Articles by E.S.T. Fernandes Articles by A. Wolfe

Proceedings of the 22nd EUROMICRO Conference

Prague, Czech Republic

September 02-September 05

ISBN: 0-8186-7487-3

	ASCII Text	x
	E.M.C. Filho, E.S.T. Fernandes, A. Wolfe, "Load Balancing in Superscalar Architectures," EUROMICRO Conference, pp. 0651, Proceedings of the 22nd EUROMICRO Conference, 1996.

	BibTex	x
	@article{ 10.1109/EURMIC.1996.546493, author = {E.M.C. Filho and E.S.T. Fernandes and A. Wolfe}, title = {Load Balancing in Superscalar Architectures}, journal ={EUROMICRO Conference}, volume = {0}, year = {1996}, isbn = {0-8186-7487-3}, pages = {0651}, doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1996.546493}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - EUROMICRO Conference TI - Load Balancing in Superscalar Architectures SN - 0-8186-7487-3 SP EP A1 - E.M.C. Filho, A1 - E.S.T. Fernandes, A1 - A. Wolfe, PY - 1996 KW - parallel architectures; superscalar architectures; load balancing; instruction-level parallelism; multiple functional units; parallel instruction execution; application program; hardware resources; processor throughput; computational load; dynamic instruction-issuing algorithm; performance; superscalar processors VL - 0 JA - EUROMICRO Conference ER -

E.M.C. Filho, COPPE, Univ. Federal do Rio de Janeiro, Brazil

E.S.T. Fernandes, COPPE, Univ. Federal do Rio de Janeiro, Brazil

A. Wolfe, COPPE, Univ. Federal do Rio de Janeiro, Brazil

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/EURMIC.1996.546493

Abstract: New techniques are increasing the degree of instruction-level parallelism exploited by processors. Recent superscalar implementations include multiple functional units, allowing the parallel execution of several instructions from the same application program. The trend towards an expansion of the number of hardware resources is likely to continue in future superscalar designs, and in order to maximize the processor throughput, the computational load must be balanced among these resources by the dynamic instruction-issuing algorithm. We investigate the effect on performance caused by the way instructions are distributed among the functional units of superscalar processors. Our results show that a performance gain of up to 38% can be obtained when the instructions are evenly distributed among the functional units.

Index Terms:

parallel architectures; superscalar architectures; load balancing; instruction-level parallelism; multiple functional units; parallel instruction execution; application program; hardware resources; processor throughput; computational load; dynamic instruction-issuing algorithm; performance; superscalar processors

Citation:

E.M.C. Filho, E.S.T. Fernandes, A. Wolfe, "Load Balancing in Superscalar Architectures," euromicro, pp.0651, Proceedings of the 22nd EUROMICRO Conference, 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.