Proceedings of the 22nd EUROMICRO Conference A Fast Capability Extension to a RISC Architecture Prague, Czech Republic September 02-September 05 ISBN: 0-8186-7487-3
Abstract: The concept of capability-based addressing originated in the 60's a means of promoting security and information sharing in computer systems; however, poor performance of early capability-based machines prevented it from becoming widespread. We describe a capability-based architecture implemented as a fairly straightforward extension of a conventional RISC architecture. Without compromising the security aspect, the capability mechanism was simplified to allow for an implementation that does not stretch the cycle time of the core architecture. Simulated executions of benchmark programs show that the performance penalty of using the capability mechanism is in the range of 16% to 19%, an acceptable price to pay for security. The proposed architecture can thus be a viable solution for meeting the increased demands for security as information sharing becomes pervasive.
Index Terms:
reduced instruction set computing; fast capability extension; RISC architecture; capability-based addressing; security; information sharing; capability-based machines; simulated executions; performance penalty
Citation:
K. Ghose, P. Vasek, "A Fast Capability Extension to a RISC Architecture," euromicro, pp.0606, Proceedings of the 22nd EUROMICRO Conference, 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||