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Proceedings of the 22nd EUROMICRO Conference
Low-Power Embedded Microprocessor Design
Prague, Czech Republic
September 02-September 05
ISBN: 0-8186-7487-3
ASCII Text
x 
 
C. Piguet, T. Schneider, J.-M. Masgonty, C. Arm, S. Durand, M. Stegers, "Low-Power Embedded Microprocessor Design," EUROMICRO Conference, pp. 0600, Proceedings of the 22nd EUROMICRO Conference, 1996.
 
 
BibTex
x
 
@article{ 10.1109/EURMIC.1996.546487,
author = {C. Piguet and T. Schneider and J.-M. Masgonty and C. Arm and S. Durand and M. Stegers},
title = {Low-Power Embedded Microprocessor Design},
journal ={EUROMICRO Conference},
volume = {0},
year = {1996},
isbn = {0-8186-7487-3},
pages = {0600},
doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1996.546487},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - EUROMICRO Conference
TI - Low-Power Embedded Microprocessor Design
SN - 0-8186-7487-3
SP
EP
A1 - C. Piguet,
A1 - T. Schneider,
A1 - J.-M. Masgonty,
A1 - C. Arm,
A1 - S. Durand,
A1 - M. Stegers,
PY - 1996
KW - microprocessor chips; low-power embedded microprocessor design; CMOS technology; low-power RISC-like architectures; clock cycles; power savings; gated clock techniques; hierarchical memories
VL - 0
JA - EUROMICRO Conference
ER -
 
C. Piguet, Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
T. Schneider, Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
J.-M. Masgonty, Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
C. Arm, Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
S. Durand, Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
M. Stegers, Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
Abstract: Low-power consumption has emerged as a very important issue in the design of integrated circuits in CMOS technology. The basic idea behind low-power RISC-like architectures is to reduce the number of executed instructions and clock cycles for the execution of a given task. In addition to these architectural issues, important power savings have been obtained by lowering the supply voltage, by pipelining, by adopting gated clock techniques as well as by using hierarchical memories.
Index Terms:
microprocessor chips; low-power embedded microprocessor design; CMOS technology; low-power RISC-like architectures; clock cycles; power savings; gated clock techniques; hierarchical memories
Citation:
C. Piguet, T. Schneider, J.-M. Masgonty, C. Arm, S. Durand, M. Stegers, "Low-Power Embedded Microprocessor Design," euromicro, pp.0600, Proceedings of the 22nd EUROMICRO Conference, 1996
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