Proceedings of the 22nd EUROMICRO Conference An FPGA-Based Square-Root Co-Processor Prague, Czech Republic September 02-September 05 ISBN: 0-8186-7487-3
Abstract: In this paper we present a FPGA implementation of non-restoring integer square-root algorithm, that use estimates for the result-digit selection and radix-2 redundant addition in recurrence. On-the-fly conversion of the result- digit and signed-digit adder/subs tractor are used to simplify hardware realization. Modifications of equations for optimal Xilinx CLBs utilization as well as necessary CLR resources for different bit-lengths calculations are outlined, concerning XC3000 family
Citation:
V. Tchoumatchenko, T. Vassileva, P. Gurov, "An FPGA-Based Square-Root Co-Processor," euromicro, pp.0520, Proceedings of the 22nd EUROMICRO Conference, 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||