Proceedings of the 22nd EUROMICRO Conference
SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation
Prague, Czech Republic
September 02-September 05
ISBN: 0-8186-7487-3
R. Bevacqua, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
L. Guerrazzi, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
F. Fummi, Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
Abstract: Test pattern storage is an important problem affecting all Design for Testability (DfT) techniques based on scan-path. Built-In Self Test (BIST) methodologies are used in conjunction to scan-path techniques for reducing the amount of test patterns that must be stored. This paper analyzes two SCAN/BIST approaches and identifies conditions which guarantee that such techniques require shorter test sequences in relation to a simple scan method. Such conditions concern the ability of sequential test pattern generators (TPGs) to concatenate test sequences, but, unfortunately, standard sequential TPGs do not show sufficient capabilities in this task. This, the paper presents an innovative concatenation strategy for test sequences based on implicit techniques. Preliminary results and a case-study show that the use of the presented SCAN/BIST approaches, with the proposed test generation strategy, generates a test methodology that sensibly reduce the amount of test patterns which must be stored.
Index Terms:
design for testability; Design for Testability; test storage; test pattern generation; SCAN; BIST; Built-In Self Test; scan-path techniques; test sequences
Citation:
R. Bevacqua, L. Guerrazzi, F. Fummi, "SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation," euromicro, pp.0351, Proceedings of the 22nd EUROMICRO Conference, 1996