Abstract: Up to now, strategies for behavioral fault modeling and testing are based on an adaptation of the gate-level strategies to generate test data at the behavioral level. In other words, they explore the impact of low-level faults on the behavioral fault modeling and detection. In this paper, we explore the dual approach, i.e. the impact of high-level fault detection on gate-level fault detection. Due to the great development of both design automation tools and hardware description languages such as VHDL or VERILOG which allow to specify a hardware system as a software program, behavioral faults are considered as software faults and the mutation-based testing, originally proposed to test software programs, is adapted to generate test data for VHDL descriptions. The generated test set is used to validate the VHDL description, seen as a software program, against (software) design faults as well as its hardware implementation against hardware faults. To validate the approach, the gate-level fault coverage of the generated test set is computed and compared to traditional ATPG's result.